1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a manufacturing method thereof and more particularly to a test facilitating design method capable of reducing the overhead by mounting a testing circuit in the semiconductor integrated circuit device. The present invention also relates to a technique effective for application to, for example, a microprocessor and a one-chip microcomputer including a CPU (Central Processing Unit) and a writable memory circuit in which an operation program for the CPU is stored.
2. Description of the Related Art
Generally, in a case of a test facilitating design method in a logic LSI named a system LSI having a CPU, a RAM (Random Access Memory) and the like mounted or integrated therein, a scan path method is commonly used for testing logical states of an internal logic circuit, with it operated, constituting flip-flop circuits connected in series by supplying test data to the internal logic circuit. The scan path method has about 35% overhead of hardware and a failure detection ratio thereof is only about 85%.
Further, in addition to the scan path method, there is a BIST (Built-In Self-Test) method including a random pattern generator and a signature compressor mounted in a chip as a testing circuit. The BIST method is different from the logical verification using a test pattern generated in accordance with a failure detection algorithm used in the scan path method and uses a random test pattern. Moreover, recently, in a semiconductor memory such as a RAM, there is proposed a technique named a so-called memory BIST in which a predetermined test pattern is generated in accordance with a predetermined algorithm within a chip to detect a defective bit.
However, even when the BIST method is adopted, it is necessary to connect a high-speed and high-function tester thereto as used in the scan path method and perform measurement in accordance with control instructed from the tester. In the test performed by the BIST circuit, since the expensive tester is often waited in mere waiting time processing, the cost required for the test is not reduced.
For this reason, inventors have proposed a technique so-called xe2x80x9clogic with test functionxe2x80x9d for self-testing the logic with a logic tester constituted in a chip, which is a measuring manner with a test circuit built-in chip that is different from BIST. This method can reduce the cost required for the test greatly since it is not necessary to use an expensive tester, although there has a large overhead of hardware and the yield of product is reduced due to failure of a testing circuit itself mounted in a chip similarly to the BIST method.
In order to solve this problem, the inventors have before proposed a technique named a so-called xe2x80x9ctesting method without overheadxe2x80x9d that an FPGA (Field Programmable Gate Array) is provided in a chip to configure an ALPG (Algorithmic Pattern Generator) by the FPGA so that a test pattern is generated in accordance with a predetermined algorithm to perform a test and a usual logic circuit is re-configured in the FPGA after completion of the test (International Publication WO 00/62339).
In this technique, a circuit named a so-called self-verification type FPGA capable of detecting its own defect is provided in a user logic circuit to configure a testing circuit therein to test itself and a user circuit is provided in the FPGA finally to reduce the overhead of hardware caused by the provision of the testing circuit. The method is characterized in that since the FPGA constitutes the self-verification type circuit, a defective portion can be detected by itself to output information concerning the defective portion to the outside so that the circuit can be configured with the exception of the defective portion when a logic tester is configured in the FPGA by means of the tester HDL (Hardware Description Language) or when a user circuit is configured in the FPGA and accordingly reduction of the yield can be avoided.
In the above method, however, it is necessary to introduce a process for a new device named the FPGA and semiconductor makers providing the FPGAs or products having the FPGA mounted therein to the market can realize the user circuit including the FPGA by slight modification of processes, although there is an impediment that general semiconductor makers do not usually manufacture the FGPAs or the products having the FPGA mounted therein and it is necessary to design the FPGA and develop a new process for fabricating the FPGA on a semiconductor chip for the purpose of the development of this method.
Furthermore, even when the aforementioned test facilitating design technique is applied to configure the testing circuit within the chip, only an internal circuit can be tested by the testing circuit and a test as to whether an input/output circuit for outputting a signal to an external terminal and taking in a signal externally is operated normally or not must be performed by means of a tester.
It is an object of the present invention to provide a test technique of a semiconductor integrated circuit device capable of performing test with high accuracy without using an expensive tester.
It is another object of the present invention to provide a test technique suitable for a semiconductor integrated circuit device such as a microprocessor and a one-chip microcomputer including a CPU and a writable memory circuit for storing an operation program thereof.
The above and other objects and novel features of the present invention will be apparent from the following description and the accompanying drawings of the specification.
Representatives of the inventions disclosed in the present application are summarized as follows.
That is, a manufacturing method of a semiconductor integrated circuit device comprises the steps of providing wiring conductors capable of connecting between any of chips or devices and variable switch circuits capable of connecting between predetermined wiring conductors on a wafer in which microprocessor-included chips or microcomputer-included chips including a CPU and a writable memory circuit for storing an operation program of the CPU are formed or on a testing board in which microprocessor-included devices or microcomputer-included devices packed into packages are mounted, writing a testing program into a writable memory circuit capable of being used as a program storage area in any one of chips or devices, and executing the testing program by the CPU of that any one of chips or devices to thereby test a testing chip or device and a chip or device to be tested.
According to the above configuration of the present invention, since the chip or device on the wafer or board can be used to test another chip or device, the test or part of the test similar to that performed by a conventional tester can be made by means of a burn-in apparatus or an aging apparatus without using an expensive tester to thereby reduce a cost of the test.
The test performed by the testing program is to test transmission and reception operation of signals between any one of chips or devices and another chip or device. Since it is possible to detect that the input/output circuit of any of two chips or devices connected for the purpose of the test on the wafer or board is defective or the input/output circuit of any of chips is normal, the chip or device having the input/output circuit judged as normal can be used as a testing circuit to test remaining chips or devices on the wafer or board, so that judgment as to whether the chips or devices are good or defective can be performed efficiently.
Further, preferably, a self-testing circuit for testing an internal circuit is provided within the microprocessor-built-in chip or microcomputer-built-in chip or device and after the internal circuit is tested by the self-testing circuit, the input/output circuit is tested by means of transmission and reception of signals between the any of chips. Accordingly, the whole of chip or device including the internal circuit can be tested without using an expensive tester to thereby reduce the cost required for the test.
Moreover, preferably, the internal circuit is divided into a plurality of functional blocks and the self-testing circuit is provided in each of the functional blocks. After the functional block has been tested by the self-testing circuit corresponding thereto, the input/output circuit is tested by means of transmission and reception of signals between the any of chips. Although when the scale of logic in the chip or device is increased, a test pattern of the self-testing circuit for testing the chip or device is made complicated and very large and a test time is lengthened, the division of the internal circuit into a plurality of functional blocks and the provision of the self-testing circuit in each of the functional blocks can simplify the test pattern and can operate a plurality of self-testing circuits in parallel to perform the test, so that the test time can be shortened.
Further, the wiring conductors capable of connecting between the any of chips and the variable switch circuits capable of connecting between the predetermined wiring conductors are disposed in a chip dividing area of the wafer. Consequently, the above test can be performed without increase of the overhead of hardware.
Furthermore, the wiring conductors capable of connecting between the any of chips are disposed in the whole area of the wafer and the variable switch circuits capable of connecting between the wiring conductors are disposed in a chip dividing area of the wafer. Thus, even if the number of chips on the wafer is increased, the hardware capable of performing the above test can be provided in the chip dividing area having the substantially same area as the chip dividing area on the conventional wafer.
Moreover, the test of the internal circuit or the functional block by the self-testing circuit and the test of the input/output circuit by means of transmission and reception of signals between any of chips are performed by a burn-in apparatus or an aging apparatus in a state where the chips are mounted on the wafer. Consequently, the burn-in test and the functional test of the chips or devices can be performed at the same time and the test time can be shortened greatly to thereby reduce the cost required for the test.
In addition, the testing program written in the memory circuit within the chip is described in a C-language used in a virtual tester. Consequently, when a microprocessor-built-in device or a microcomputer-built-in device is developed newly, it is not necessary to prepare a dedicated testing program in order to test the input/output circuit by means of transmission and reception of signals between chips or devices, so that a development term of a new product can be shortened.